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d a t a sh eet product specification supersedes data of 2003 apr 04 2004 apr 22 integrated circuits uda1380 stereo audio coder-decoder for md, cd and mp3
2004 apr 22 2 nxp semiconductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 contents 1 features 1.1 general 1.2 multiple format data input interface 1.3 multiple format data output interface 1.4 adc front-end features 1.5 dac features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 clock modes 8.2 adc analog front-end 8.3 decimation filter (adc) 8.4 interpolation filter (dac) 8.5 noise shaper 8.6 fsdac 8.7 headphone driver 8.8 digital and analog mixers (dac) 8.9 application modes 8.10 power-on reset 8.11 power-down requirements 8.12 plop prevention 8.13 digital audio data input and output 9 l3-bus interface description 9.1 introduction 9.2 device addressing 9.3 slave address 9.4 register addressing 9.5 data write mode 9.6 data read mode 10 i 2 c-bus interface description 10.1 addressing 10.2 write cycle 10.3 read cycle 11 register mapping 11.1 evaluation modes and clock settings 11.2 i 2 s-bus input and output settings 11.3 power control settings 11.4 analog mixer settings 11.5 headphone amplifier settings 11.6 master volume control 11.7 mixer volume control 11.8 mode, bass boost and treble 11.9 master mute, channel de-emphasis and mute 11.10 mixer, silence detector and oversampling settings 11.11 decimator volume control 11.12 pga settings and mute 11.13 adc settings 11.14 agc settings 11.15 restore l3 default values (software reset) 11.16 headphone driver and interpolation filter (read-out) 11.17 decimator read-out 12 limiting values 13 handling 14 thermal characteristics 15 quality specification 16 dc characteristics 17 ac characteristics 18 timing 19 application information 20 package outlines 21 soldering 21.1 introduction to soldering surface mount packages 21.2 reflow soldering 21.3 wave soldering 21.4 manual soldering 21.5 suitability of surface mount ic pa ckages for wave and reflow soldering methods 22 data sheet status 23 disclaimers 24 trademarks
2004 apr 22 3 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 1 features 1.1 general ? 2.4 to 3.6 v power supply ? 5 v tolerant digital inputs (at 2.7 to 3.6 v power supply) ? 24-bit data path for analog-to-digital converter (adc) and digital-to-analog converter (dac) ? selectable control via l3-bus microcontroller interface or i 2 c-bus interface; choice of 2 device addresses in l3-bus and i 2 c-bus mode remark : this device does not have a static mode. ? supports sample frequencies from 8 to 55 khz for the adc part, and 8 to 100 khz for the dac part. the adc does not support dvd audio (96 khz audio), only mini-disc (md), compact-disc (cd) and moving picture experts group layer-3 audio (mp3). for playback 8 to 100 khz is specified. dvd playback is supported ? power management unit: ? separate power control for adc, automatic volume control (avc), dac, phase locked loop (pll) and headphone driver ? analog blocks like adc and programmable gain amplifier (pga) have a block to power-down the bias circuits ? when adc and/or dac are powered-down, the clocks to these blocks are also stopped to save power. remark: by default, when the ic is powered-up, the complete chip will be in the power-down mode. ? adc part and dac part can run at different frequencies, either system clock or word select pll (wspll) ? adc and pga plus integrated high-pass filter to cancel dc offset ? the decimation filter is equipped with a digital automatic gain control (agc) ? mono microphone input with low noise amplifier (lna) of 29 db fixed gain and variable gain amplifier (vga) from 0to30db in steps of 2db ? integrated digital filter plus dac ? separate single-ended line output and one stereo headphone output, capable of driving a 16 load. the headphone driver has a built-in short-circuit protection with status bits which can be read out from the l3-bus or i 2 c-bus interface ? digital silence detection in the interpolator (playback) with read-out status via l3-bus or i 2 c-bus interface ? easy application. 1.2 multiple format da ta input interface ? slave bck and ws signals ? i 2 s-bus format ? msb-justified fo rmat compatible ? lsb-justified format compatible. 1.3 multiple format data output interface ? select option for digital ou tput interface: either the decimator output (adc signal) or the output signal of the digital mixer which is in the interpolator dsp ? selectable master or slave bck and ws signals for digital adc output remark : sysclk must be applie d in wspll mode and master mode ? i 2 s-bus format ? msb-justified fo rmat compatible ? lsb-justified format compatible. 1.4 adc front-end features ? adc plus decimator can run at either wspll, regenerating the clock from wsi signal, or on sysclk ? stereo line input with pga: gain range from 0to24db in steps of 3 db ? lna with 29 db fixed gain for mono microphone input, including vga with gain from 0 to 30 db in steps of 2 db ? digital left and right independent volume control and mute from +24 to ? 63.5 db in steps of 0.5 db.
2004 apr 22 4 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 1.5 dac features ? dac plus interpolator can run at either wspll (regenerating the clock from wsi) or at sysclk ? separate digital logarithmic volume control for left and right channels via l3-bus or i 2 c-bus from 0 to ? 78 db in steps of 0.25 db ? digital tone control, bass boost and treble via l3-bus or i 2 c-bus interface ? digital de-emphasis for sample frequencies of: 32, 44.1, 48 and 96 khz via l3-bus or i 2 c-bus interface ? cosine roll-off soft mute function ? output signal polarity control via l3-bus or i 2 c-bus interface ? digital mixer for mixing adc output signal and digital serial input signal, if they run at the same sampling frequency. 2 applications this audio coder-decoder is suitable for home and portable applications like md, cd and mp3 players. 3 general description the uda1380 is a stereo audio coder-decoder, available in tssop32 (uda1380tt) and hvqfn32 (uda1380hn) packages. all functions and features are identical for both package versions. the term ?uda1380? in this document refers to both uda1380tt and uda1380hn, unless particularly specified. the front-end of the uda1380 is equipped with a stereo line input, which has a pga control, and a mono microphone input with an lna and a vga. the digital decimation filter is equipped with an agc which can be used in case of voice-recording. the dac part is equipped with a stereo line output and a headphone driver output. the headphone driver is capable of driving a 16 load. the headphone driver is also capable of driving a headphone without the need for external dc decoupling capacitors, since the headphone can be connected to a pin v ref(hp) on the chip. in addition, there is a built-in short-circuit protection for the headphone driver output which, in case of short-circuit, limits the current through the operational amplifiers and signals the event via its l3-bus or i 2 c-bus register. the uda1380 also supports an application mode in which the coder-decoder itself is not running, but an analog signal, for instance coming from an fm tuner, can be controlled in gain and applied to the output via the headphone driver and line outputs. the uda1380 supports the i 2 s-bus data format with word lengths of up to 24 bits, the msb-justified data format with word lengths of up to 24 bits and the lsb-justified serial data format with word lengths of 16, 18, 20 or 24 bits (lsb-justified 24 bits is only supported for the output interface). the uda1380 has sound processing features in playback mode, de-emphasis, volume, mute, bass boost and treble which can be controlled by the l3-bus or i 2 c-bus interface.
2004 apr 22 5 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 4 quick reference data v ddd =v dda(ad) =v dda(da) =v dda(hp) =3.0v; t amb =25 c; r l =5k ; all voltages measured with respect to ground; unless otherwise specified. symbol parameter conditions min. typ. max. unit supplies v dda(ad) adc analog supply voltage 2.4 3.0 3.6 v v dda(da) dac analog supply voltage 2.4 3.0 3.6 v v dda(hp) headphone analog supply voltage note 1 2.4 3.0 3.6 v v ddd digital supply voltage 2.4 3.0 3.6 v i dda(ad) adc analog supply current one adc and microphone amplifier enabled; f s =48khz ? 4.5 ? ma two adcs and pga enabled; f s =48khz ? 7.0 ? ma all adcs and pgas power-down, but avc activated; f s =48khz ? 3.3 ? ma all adcs, pgas and lna power-down; f s =48khz ? 1.0 ? a i dda(da) dac analog supply current operating mode; f s =48khz ? 3.4 ? ma power-down mode; f s =48khz ? 0.1 ? a i dda(hp) headphone analog supply current no signal applied (quiescent current) ? 0.9 ? ma power-down mode ? 0.1 ? a i ddd digital supply current operating mode; f s =48khz ? 10.0 ? ma playback mode; f s =48khz ? 5.0 ? ma record mode; f s =48khz ? 6.0 ? ma power-down mode; f s =48khz ? 1.0 ? a i dd(tot) total supply current playback mode (without headphone); f s =48khz ? 8 ? ma playback mode (with headphone); no signal; f s =48khz ? 9 ? ma record mode (audio); f s =48khz ? 13 ? ma record mode (speech); f s =48khz ? 10 ? ma record mode (audio and speech); f s =48khz ? 13 ? ma fully operating; f s =48khz ? 23 ? ma signal mix-in operating, using fsdac, avc (with headphone); no signal; f s =48khz ? 12 ? ma power-down mode; f s =48khz ? 2 ? a t amb ambient temperature ? 40 ? +85 c
2004 apr 22 6 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 analog-to-digital conver ter (supply voltage 3.0 v) d o digital output level at 0 db setting; v i(rms) =1.0v ? 1.5 ? 1 ? 0.5 dbfs (thd+n)/s 48 total harmonic distortion- plus-noise to signal ratio at f s =48khz at ? 1dbfs ?? 85 ? 80 db at ? 60 dbfs; a-weighted ?? 37 ? 32 db s/n 48 signal-to-noise ratio at f s =48khz v i = 0 v; a-weighted 92 97 ? db cs channel separation ? 100 ? db lna input plus analog-to-digital converter (supply voltage 3.0 v) v i(rms) input voltage (rms value) at 0 dbfs digital output; 2.2 k source impedance ?? 35 mv (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db ?? 74 ? db at ? 60 db; a-weighted ?? 25 ? db s/n 48 signal-to-noise ratio at f s =48khz v i = 0 v; a-weighted ? 85 ? db cs channel separation ? 70 ? db digital-to-analog converter (supply voltage 3.0 v) v o(rms) output voltage (rms value) at 0 dbfs digital input; note 2 ? 0.9 ? v (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db ?? 85 ? 80 db at ? 60 db; a-weighted ?? 40 ? 35 db (thd+n)/s 96 total harmonic distortion-plus-noise to signal ratio at f s =96khz at 0 db ?? 80 ? 75 db at ? 60 db; a-weighted ?? 37 ? 32 db s/n 48 signal-to-noise ratio at f s =48khz code = 0; a-weighted 95 100 ? db s/n 96 signal-to-noise ratio at f s =96khz code = 0; a-weighted 92 97 ? db cs channel separation ? 90 ? db avc (line input via adc input; output on line output and headphone driver; supply voltage 3.0 v) v i(rms) input voltage (rms value) ? 150 ? mv (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db ?? 80 ? db at ? 60 db; a-weighted ?? 28 ? db symbol parameter conditions min. typ. max. unit
2004 apr 22 7 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 notes 1. when the supply voltages are below 2.7 v and the headphone load impedance is 16 , it is recommended to limit the dac and the headphone output to less than -2db; otherwise clipping may occur. 2. the output voltage of the dac is proportional to the dac power supply voltage. 3. channel separation performance is measured at the ic pin. 5 ordering information s/n 48 signal-to-noise ratio at f s =48khz v i = 0 v; a-weighted ? 87 ? db headphone driver (supply voltage 3.0 v) p o(rms) output power (rms value) at 0 dbfs digital input; r l =16 30 35 40 mw (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db; r l =16 ; note 1 ?? 60 ? 52 db at 0 db; r l =5k ?? 82 ? 77 db at ? 60 db; a-weighted ?? 33 ? 27 db s/n 48 signal-to-noise ratio at f s =48khz code = 0; a-weighted 87 93 ? db cs channel separation r l =16 using pin v ref(hp) ; no dc decoupling capacitors; note 3 55 60 ? db r l =16 single-ended application with dc decoupling capacitors (100 f typical) 63 68 ? db r l =32 single-ended application with dc decoupling capacitors (100 f typical) 69 74 ? db power consumption (supply voltage 3.0 v; f s =48khz) p tot total power dissipation playback mode (without headphone) ? 24 ? mw playback mode (with headphone) ? 27 ? mw record mode (audio) ? 39 ? mw record mode (speech) ? 30 ? mw record mode (audio and speech) ? 40 ? mw full operation ? 69 ? mw power-down mode ? 6 ? w type number package name description version uda1380tt tssop32 plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm sot487-1 uda1380hn hvqfn32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 mm sot617-1 symbol parameter conditions min. typ. max. unit
2004 apr 22 8 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 6 block diagram handbook, full pagewidth mgu526 9 (5) 31 (27) 3 (31) 5 (1) 13 (9) 7 (3) 8 (4) 10 (6) 11 (7) 12 (8) 27 (23) reset vinl vinm bcki bcko datao wsi wso datai voutl 14 (10) 17 (13) 1 (29) 16 (12) 18 (14) 19 (15) 15 (11) 25 (21) voutr l3data/sda sel_l3_iic rtcb l3clock/scl l3mode fsdac adc n.c. ana vc wspll sdc sdc mic amp l3 or i 2 c-bus interface ana vc headphone driver headphone driver v ssd v ssa(da) v dda(hp) voutrhp voutlhp v ref(hp) interpolation filter noise shaper dsp features data input interface 26 (22) v dda(da) 22 (18) 24 (20) 23 (19) 28 (24) data output interface agc dc-cancellation filter decimation filter sysclk v ssa(hp) 20 (16) 21 (17) vinr 30 (26) v ssa(ad) 32 (28) v dda(ad) 4 (32) v adcp 2 (30) v adcn 29 (25) v ref 6 (2) v ddd fsdac sdc pga pga uda1380tt (uda1380hn) + 29 db adc fig.1 block diagram. pin numbers for uda1380hn in parentheses.
2004 apr 22 9 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 7 pinning symbol pin type description uda1380tt uda1380hn vinr 1 29 analog pad adc input right, also connected to the mixer input of the fsdac v adcn 2 30 analog pad adc reference voltage vinm 3 31 analog pad microphone input v adcp 4 32 analog pad adc reference voltage reset 5 1 5 v tolerant digital input pad; push-pull; ttl with hysteresis; pull-down pin reset with pull-down, for making power-on reset (por) v ddd 6 2 digital supply pad digital supply voltage bcko 7 3 5 v tolerant digital bidirectional pad; push-pull input; 3-state output; 5 ns slew-rate control; ttl with hysteresis bit clock output wso 8 4 word select output datao 9 5 output pad; push-pull; 5 ns slew-rate control; cmos data output bcki 10 6 5 v tolerant digital input pad; push-pull; ttl with hysteresis bit clock input wsi 11 7 word select input datai 12 8 data input sysclk 13 9 system clock 256f s , 384f s , 512f s or 768f s input v ssd 14 10 digital ground pad digital ground rtcb 15 11 5 v tolerant digital input pad; push-pull; ttl with hysteresis; pull-down test control input, to be connected to digital ground in the application l3mode 16 12 5 v tolerant digital bidirectional pad; push-pull input; 3-state output; 5 ns slew-rate control; ttl with hysteresis l3-bus mode input or pin a1 for i 2 c-bus slave address setting l3clock/sc l 17 13 5 v tolerant digital input pad; push-pull; ttl with hysteresis l3-bus or i 2 c-bus clock input l3data/sda 18 14 i 2 c-bus pad; 400 khz i 2 c-bus specification l3-bus or i 2 c-bus data input and output sel_l3_iic 19 15 5 v tolerant digital input pad; push-pull; ttl with hysteresis input channel select v ssa(hp) 20 16 analog ground pad headphone ground voutrhp 21 17 analog pad headphone output right v ref(hp) 22 18 analog pad headphone reference voltage voutlhp 23 19 analog pad headphone output left v dda(hp) 24 20 analog supply pad headphone supply voltage voutr 25 21 analog pad dac output right v dda(da) 26 22 analog supply pad dac analog supply voltage voutl 27 23 analog pad dac output left
2004 apr 22 10 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 v ssa(da) 28 24 analog ground pad dac analog ground v ref 29 25 analog pad adc and dac reference voltage v ssa(ad) 30 26 analog ground pad adc analog ground vinl 31 27 analog pad adc input left, also connected to the mixer input of the fsdac v dda(ad) 32 28 analog supply pad adc analog supply voltage symbol pin type description uda1380tt uda1380hn handbook, halfpage uda1380tt mgu525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vinr v adcn vinm v adcp reset v ddd bcko wso datao bcki wsi datai sysclk v ssd rtcb l3mode v dda(ad) vinl v ssa(ad) v ref v ssa(da) voutl v dda(da) voutr v dda(hp) voutlhp v ref(hp) voutrhp v ssa(hp) sel_l3_iic l3data/sda l3clock/scl 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 fig.2 pin configuration uda1380tt. mgw778 uda1380hn transparent top view voutrh p wsi datai v ref(hp) bcki voutlh p datao v dda(hp) wso voutr bcko v dda(da) v ddd voutl reset v ssa(da) sysclk v ssd rtcb l3mode l3clock/scl l3data/sda sel_l3_iic v ssa(hp) v adcp vinm v adcn vinr v dda(ad ) vinl v ssa(ad ) v ref 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 i ndex area fig.3 pin configuration uda1380hn.
2004 apr 22 11 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8 functional description 8.1 clock modes there are two clock systems: ? a sysclk signal, comi ng from the system ? a wspll which generates the internal clocks from the incoming wsi signal. the system frequency applied to pin sysclk is selectable. the options are 256f s , 384f s , 512f s and 768f s . the system clock must be locked in frequency to the digital interface signals. remark : since there is neither a fixed reference clock available in the ic itself, nor a fixed clock available in the system the ic is in, there is no auto sample rate conversion detection circuitry. the system can run in several modes, using the two clock systems: ? both the dac and the adc part can run at the applied sysclk input. in this case the wspll is powered-down ? the adc can run at the sysclk input, and at the same time the dac part can run (at a different frequency) at the clock re-generated from the wsi signal ? the adc and the dac can both run at the clock regenerated from the wsi signal. 8.1.1 wspll requirements the wspll is meant to lock on to the wsi input signal, and regenerates 256f s and 128f s signals for the fsdac and the interpolator core (and for the decimator if needed). since the operating range of the wspll is from 75 to 150 mhz, the complete range of 8 to 100 khz sampling frequency must be divided into smaller parts, as given in table 1, using fig.4 as a reference. this means that the user must set the input range of the wsi input signal. in case the sysclk is used for clocking the complete system (decimator including interpolator) the wspll must be powered-down with bit adc_clk via the l3-bus or i 2 c-bus. the sel_loop_div[1:0] can be controlled by the pll1 and pll0 bits in the l3-bus or i 2 c-bus register. handbook, halfpage vco wsi div1 128f s (digital parts) 256f s (adc and fsdac) pre1 mgu527 fig.4 wspll set-up. table 1 wspll divider settings word select frequency (khz) sel_loop_div[1:0] pre1 div1 vco frequency (mhz) 6.25 to 12.5 00 8 1536 76 to 153 12.5 to 25 01 4 1536 25 to 50 10 2 1536 50 to 100 11 2 768
2004 apr 22 12 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8.1.2 c lock distribution figure 5 shows the main clock distribution for the sysclk domain and the wspll clock domain. for power saving reasons each clock signal inside the system must be controlled and enabled via a separate bit in the l3-bus and i 2 c-bus registers (adc_clk). the dac part of the uda1380 can operate from 8 to 100 khz sampling frequency (f s ). this applies to the dac part only; the adc part can run from 8 to 55 khz. handbook, full pagewidth decimator i 2 s-bus output block i 2 s-bus input block l3 or i 2 c-bus register decimator adc 128f s 128f s enable clock 256/384/512/768f s enable clock adc_clk clk_div sysclk wspll wsi fsdac interpolator l3 or i 2 c-bus register interpolator 128f s 128f s 256f s enable clock mgu528 enable clock dac_clk fig.5 clock routing for the main blocks inside the coder-decoder.
2004 apr 22 13 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8.2 adc analog front-end the analog front-end of the uda1380 consists of one stereo adc with a selector in front of it (see fig.6). using this selector one can either select the microphone input with the microphone amplifier (lna) with a fixed 29 db gain and vga (no pga, since a real microphone amplifier is much better with respect to noise), or the line input which has a pga for having 0 or 6 db gain (for supporting 1 and 2 v (rms) input). the pga also provides gain control from 0to24db in steps of 3db. remark : ? the input impedance of the pga (line input) is 12 k , for the lna this is 5 k 8.2.1 a pplications and p ower - down modes the following power-down modes and functional modes are supported: ? power-down mode in which the power consumption is very low (only leakage currents) in this mode there is no reference voltage at the line input ? line input mode, in which the pga can be used ? microphone mode, in which the rest of the non-used pgas and adcs are powered-down ? mixed pga and lna mode: one line input and one microphone input. more information on the analog frond-end is given in section 8.11.1. handbook, full pagewidth pga adc adc sdc mgu530 pga 31 (27) (29) (31) vinl 1 vinr 3 vinm sdc lna sdc sel_mic bitstream right bitstream left sel_lna fig.6 analog front-end. pin numbers for uda1380hn in parentheses. 8.2.2 lna with vga the lna is equipped with a vga. the function of the vga is to have additional variable analog gain from 0 to 30 db in steps of 2 db. this provides more flexibility in the choice of the microphone. 8.2.3 a pplications with 2v( rms ) input for the line input it is preferable to have 0 db and 6 db gain settings in order to be able to apply both 1 and 2 v (rms) input signals, using a series resistance. for this purpose a pga is used which has 0 to 24 db gain, in steps of 3 db.
2004 apr 22 14 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 in applications in which a 2 v (rms) input signal is used, a 12 k resistor must be used in series with the input of the adc (see fig.7). this forms a voltage divider together with the internal adc resistor and ensures that the voltage, applied to the input of the ic, never exceeds 1 v (rms). using this application for a 2 v (rms) input signal, the switch must be set to 0 db. when a 1 v (rms) input signal is applied to the adc in the same application, the gain switch must be set to 6 db. an overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in table 2; the power supply voltage is assumed to be 3 v. table 2 application modes using input gain stage 8.3 decimation filter (adc) the decimation from 128f s is performed in two stages. the first stage realizes a characteristic with a decimation factor of 16. the second stage consists of 3 half-band filters, each decimating by a factor 2. the filter characteristics are shown in table 3. table 3 decimation filter characteristics 8.3.1 o verload detection the uda1380 is equipped with an overload detector which can be read out from the l3-bus or i 2 c-bus interface. in practice the output is used to indicate whenever the output data, in either the output of the left or right channel, exceeds ? 1 db (the actual figure is ? 1.16 db) of the maximum possible digital swing. when this condition is detected output bit overflow in the l3-bus register is forced to logic 1 for at least 512f s cycles (11.6 ms at f s = 44.1 khz). this time-out is reset for each infringement. 8.3.2 v olume control the decimator is equipped with a digital volume control. this volume control is separate for left and right, and can be set with bits ml_dec [7:0 ] and bits mr_dec [7:0] via the l3-bus or i 2 c-bus interface. the range is from +24 db to ? 63.5 db and mutes in steps of 0.5 db. 8.3.3 m ute the decimator is equipped with a db-linear mute which mutes the signal in 256 steps of 0.5 db. 8.3.4 agc function the decimation filter is equipped with an agc block. this function is intended, when enabled, to keep the output signal at a constant level. the agc can be used for microphone applications in which the distance to the microphone is not always the same. the agc can be enabled via an l3-bus or i 2 c-bus bit by setting the bit to logic 1. in that case it bypasses the digital volume control. via the l3-bus or i 2 c-bus interface also some other settings of the agc, like the attack and decay settings and the target level settings, can be made. remark : the dc filter before the decimation filter must be enabled by setting the l3-bus or i 2 c-bus bit skip_dcfil to logic 0 when agc is in operation; otherwise the output will be disturbed by the dc offset added in the adc. resistor (12 k ) input gain switch maximum input voltage present 0 db 2 v (rms) 6db 1v(rms) absent 0 db 1 v (rms) 6db 0.5v(rms) handbook, halfpage mgu529 v ref v dda = 3 v vinl, vinr 31, 1 (27, 29) pga 12 k external resistor 12 k input signal 2 v (rms) fig.7 adc front-end wi th pga (line input). pin numbers for uda1380hn in parentheses. x sin x ----------- item condition value (db) pass-band ripple 0 to 0.45f s 0.01 stop band >0.55f s ? 70 dynamic range 0 to 0.45f s >135 digital output level at 0 db input analog ? 1.5
2004 apr 22 15 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8.4 interpolation filter (dac) the interpolation digital filter interpolates from 1 to 64f s or to 128f s , by cascading fir filters, see table 4. the interpolator is equipped with several sound features like volume control, mute, de-emphasis and tone control. table 4 interpolation filter characteristics 8.4.1 digital mute muting the dac will result in a cosine roll-off soft mute, using 4 32 = 128 samples in normal mode (or 3 ms at 44.1 khz sampling frequency). the cosine roll-off curve is illustrated in fig.8. these cosine roll- off functions are implemented for both the digital mixer and the master mute inside the dac data path, see section 8.8. 8.4.2 s ound features in addition, there are basic sound features: ? db-linear volume control usin g 14-bit coefficients in steps of 0.25 db: range 0 to ? 78 db maximum suppression and ? db: applies to both master volume and mixing volume control ? de-emphasis for 32, 44.1, 48 and 96 khz for both channel 1 and 2 (selectable independently) ? treble, which is se lectable gain for high frequencies (positive gain only), the edge frequency of the treble is fixed (depends on the sampling frequency). can be set for left and right independently: ? two settings: f c = 1.5 khz and f c = 3 khz, assuming sampling frequency is 44.1 khz ? both settings have 0 to 6 db gain range in steps of 2 db ? bass boost, which is selectab le gain for low frequencies (positive gain only). the edge frequency of the bass boost is fixed and depends on the sampling frequency. can be set for left and right independently: ?two settings: f c = 250 hz and f c = 300 hz, assuming sampling frequency is 44.1 khz ? first setting: 0 to 18 db ga in range in steps of 2 db ? second setting: 0 to 24 db gain range in steps of 2 db. 8.5 noise shaper the noise shaper consists of two mono 3rd-order noise shapers and one time-multiplexed stereo 5th-order noise shaper. the order of the noise shaper can be chosen between 3rd-order (which runs at 128f s ) and 5th-order (which runs at 64f s ) via bit sel_ns in the l3-bus or i 2 c-bus register. the preferable choice for the noise shaper order is: ? 3rd-order noise shaper is preferred at low sampling frequencies, for instance between 8 and 32 khz. this is for preventing out-of-band noise from the noise shaper to move into the audio band ? 5th-order noise shaper is normally used at higher sampling frequencies, normally from 32 to 100 khz. the noise shaper shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using an fsdac. item condition value (db) pass-band ripple 0 to 0.45f s 0.025 stop band >0.55f s ? 60 dynamic range 0 to 0.45f s >135 handbook, halfpage 010 51525 1 0 0.8 mgu119 20 0.6 0.4 0.2 t (ms) mute factor fig.8 mute as a function of raised cosine roll-off, displayed assuming 44.1 khz.
2004 apr 22 16 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8.6 fsdac 8.6.1 g eneral information the filter-stream digital-to-analog converter (fsdac) is a semi-digital reconstruction filter that converts the 1-bit data stream (running at either 64f s for the 5th-order noise shaper or 128f s for the 3rd-order noise shaper) of the noise shaper into an analog output voltage. the filter coefficients are implemented as current sources, and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity are achieved. a post-filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal, capable of driving a line output. the output voltage of the fsdac scales proportionally with the power supply voltage. remark: when the fsdac is powered-down, the output of the fsdac becomes high impedance. 8.6.2 a nalog mixer input the fsdac has a mixer input, wh ich makes it possible to mix an analog signal to the output signal of the fsdac itself. in schematic form this is given in fig.9. this mixer input can be used for instance for mixing-in a gsm signal or an fm signal directly to the line output. in the uda1380, the mixer in put is connected from the adc line input via an avc unit. remark : before the avc unit can be used stand-alone, meaning without the digital part running, first the dac part must be initialised in orde r to have the dac output generating zero current. ot herwise the signal will be clipped. 8.7 headphone driver the uda1380 is equipped with a headphone driver which can deliver 35 mw (at 3.0 v power supply) into a 16 load. the headphone driver does not need external dc decoupling capacitors because it can be dc coupled with respect to a special headphone output reference voltage. this saves two external capacitors (which is quite useful in a portable device). the headphone driver is equipped with short-circuit protection on all three operational amplifiers (left, right and the virtual ground). each of the operational amplifiers has a signalling bit which becomes lo gic 1 in case the limiter is activated, for instan ce in case of a short-circuit. this means the microcontroller in the system can poll the l3-bus or i 2 c-bus register of the headphone driver and as soon as (and for as long as) the short-circuit detection bits are activated, the microcontroller can signal the user that something is wrong or power-down the headphone driver (for instance, for energy-saving purposes). remark: to improve headphone channel separation performance, the distance between v ref(hp) and the micro speaker port must be minimized. 8.8 digital and analog mixers (dac) 8.8.1 d igital mixer the adc output signal and digital input signal can be mixed without external dsp as shown in fig.10. this mixer can be controlled via the microcontroller interface, and must only be enabled when the adc and the dac are running at the same frequency. in addition, the mixer output signal can also be applied to the i 2 s-bus output interface. handbook, halfpage mgu531 fsdac to analog mixer input bitstream fig.9 mixing signals to the fsdac output (analog domain).
2004 apr 22 17 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 handbook, full pagewidth mgu532 bass-boost and treble volume and mute de-emphasis volume and mute interpolation filter i 2 s-bus output block master sel_source 2f s 1f s volume and mute de-emphasis mixing before sound features mixing after sound features from digital data input (channel 1) data from decimation filter (channel 2) to inter- polation filter fig.10 digital mixer (dac). 8.8.2 a nalog mixer the analog mixer, which uses the mixer input of the fsdac, can mix a signal into the fsdac output signal via an avc unit (see fig.11). the mixer can be used to mix a signal into the fsdac output signal and play it via the headphone driver without the complete coder-decoder running. the analog control range is 0 to ? 64.5 db with a gain of 16.5 db, and mutes in steps of 1.5 db (so actually the range is from +16.5 db to ? 48 db plus mute). handbook, full pagewidth mgu533 resistor network avc[5:0] l3 or i 2 c-bus control bits enable mixer (en_avc) to fsdac mixer input pon_avc from analog front-end fig.11 analog mixer configuration.
2004 apr 22 18 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8.9 application modes the operation mode can be set with pin sel_l3_iic, either to l3-bus mode (low) or to the i 2 c-bus mode (high) as given in table 5. for all features in microcontroller mode see chapter 9. table 5 pin function in the selected mode remark : in the i 2 c-bus mode there is a bit a1 which sets the lsb bit of the address of the uda1380. in l3-bus mode this bit is not available, meaning the device has only one l3-bus device address. 8.10 power-on reset the uda1380 has a dedicated reset pin, which has a pull-down resistor. this way a power-on reset circuit can be made with a capacitor and a resistor at the pin. the internal pull-down resistor cannot be used because of the 5 v tolerant nature of the pad. the pull-down resistor is shielded from the outside world by a transmission gate in order to support 5 v tolerance. the reset timing is determined by the external capacitor and resistor which are conn ected to pin reset, and the internal pull-down resistor. on power-on reset, all the digital sound processing features and the system controlling features are set to the default setting of the l3-bus and i 2 c-bus control modes. remark : the reset time should be at least 1 s, and during the reset time the system clock should be running. in case the wspll is selected as the clock source, a clock must be connected to the sysclk input in order to have a proper reset of the l3-bus or i 2 c-bus registers. this is because the clock source is set to sysclk by default. 8.11 power-down requirements the following blocks have power-down control via the l3-bus or i 2 c-bus interface: ? microphone amplifier (lna) including its single-ended to differential converter (sdc) and vga ? adc plus sdc and the pga, for left and right separate ? bias generation circuit for the front-end and the fsdac ? headphone driver ? wspll ? fsdac. clocks of the decimator, interpolator and the analog blocks have separate enable and disable controls. pin l3-bus mode sel_l3_iic = l i 2 c-bus mode sel_l3_iic = h l3clock/scl l3clock scl l3mode l3mode a1 l3data/sda l3data sda
2004 apr 22 19 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8.11.1 a nalog front - end figure 12 shows the power control inside the analog front-end. the control of all power-on pins of the adc front-end is done via separate l3-bus or i 2 c-bus bits. handbook, full pagewidth pga pga_gainctrlr pga_gainctrll adc bitstream right adc sdc bitstream left mgu534 pga vinl vinr vinm sdc lna sdc pon_pgal pon_adcl pon_bias fe bias v ref pon_pgar pon_adcr pon_lna 31 (27) (29) (31) 1 3 fig.12 analog front-end power-down. pin numbers for uda1380hn in parentheses. 8.11.2 fsdac power control the fsdac block has power-on pins: one of which shuts down the dac itself, but le aves the output still at v ref voltage (which is half the powe r supply). this function is set by the bit pon_dac in the l3-bus or i 2 c-bus register. a second l3-bus or i 2 c-bus bit shuts down the complete bias circuit of the fsdac, via bit pon_bias in the l3-bus or i 2 c-bus register. this bit pon_bias acts the same as given in fig.12 for the analog front-end. 8.12 plop prevention plops are ticks and other strange sounds that can occur when a part of a device is powered-up or powered-down, or when switching between modes is done. some ways to prevent plops from occurring are: ? when the fsdac or headphone driver must be powered-down, first a digital mute is applied. after that the fsdac or headphone driver can be powered-down. in case the fsdac or headphone driver must be powered-up, first the analog part is switched on, then the digital part is demuted ? when the adc must be powered-down, a digital mute sequence must be applied. when the digital output signal is completely muted, the adc can be powered-down. in case the adc must be powered-up, first the analog part must be powered-up, then the digital part must be demuted ? when there is a change of, for example, clock divider settings or clock source (selecting be tween sysclk and wspll clock), then also digital mute for that block (either decimator or interpolator) should be used. remark : all items mentioned in section 8.12 are not ?hard-wired? implemented, but are to be followed by the user as a guideline for plop prevention.
2004 apr 22 20 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8.13 digital audio da ta input and output the supported audio formats for the control modes are: ? i 2 s-bus ? msb-justified ? lsb-justified, 16 bits ? lsb-justified, 18 bits ? lsb-justified, 20 bits ? lsb-justified, 24 bits (only for the output interface). the bit clock bck can be up to 128f s , or in other words the bck frequency is 128 times the ws frequency or less: f bck 128f ws . remark : the ws edge must coincide with the negative edge of the bck at all times, for proper operation of the digital i/o data interface. figure 13 shows the interface signals. 8.13.1 d igital audio input interface the digital audio input interface is slave only, meaning the system must provide the wsi and bcki signals (next to the datai signal). either the wspll locks onto the wsi signal and provides the internal clocks for the interpolator and the fsdac, or a system clock must be applied which must be in frequency lock to the digital data input interface signals. 8.13.2 d igital audio output interface the digital audio output interface can be either master or slave. the data source for the data output can be selected from either the decimator (adc front-end) or the digital mixer output. remark: the digital mixer output is only valid if both the decimator and the interpolator run at the same clock: ? in slave mode the signals on pins bcko, wso and sysclk must be applied from the application (signals must be in frequency lock) and the uda1380 returns the datao signal from the decimator. the applied signal from pin bcko can be for instance: 32f s , 48f s , 64f s , 96f s or 128f s ? in master mode the sysclk signal must be applied from the system, then the uda1380 returns with the bcko, wso and the datao signals. for the bcko clock, there are 2 general rules: ? when the sysclk is either 256f s or 512f s , the bcko frequency is 64f s ? when the sysclk is either 384f s or 768f s , the bcko signal is 48f s . the slave and master modes can be selected by the bit serial interface mode (sim) in the l3-bus or i 2 c-bus interface. 9 l3-bus interface description the uda1380 has an l3-bus microcontroller interface mode. controllable system and digital sound processing features are: ? software reset ? system clock frequency (selection between 256f s , 384f s , 512f s and 768f s clock divider settings) ? clock mode setting, for instance, which block runs at which clock, and clock enabling ? power control for the wspll ? data input and data output format control, for input and output independently including data source selection for the digital output interface ? adc features: ? digital mute ? agc enable and settings ? polarity control ? input line amplifier contro l (0 to 24 db in steps of 3db) ? dc filtering control ? digital gain control (+24 to ? 63 db gain in steps of 0.5 db) for left and right ? power control ? vga of the microphone input ? selection of line or microphone input. ? dac and headphone driver features: ? power control fsdac and headphone driver ? polarity control ? mixing control (only available when both decimator and interpolator run at the same speed). this includes the mixer volumes, mute and mixer position switch ? de-emphasis control ? master volume and balance control ? flat/minimum/maximum sett ings for bass boost and treble ? tone control: bass boost and treble ? master mute control ? headphone driver short-circuit protection status bits.
2004 apr 22 21 nxp semiconductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 an dbook, full pagewidth 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits w s b ck d ata right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb msb msb b2 2 1 > = 8 12 3 left i 2 s-bus format ws bck d ata right 3 > = 8 msb b2 mbl12 1 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits w s b ck d ata right 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 left lsb-justified format 16 bits w s b ck d ata right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb 16 msb b2 b3 b4 left lsb-justified format 18 bits w s b ck d ata right 15 18 17 2 1 msb b2 b3 b4 b17 lsb 16 15 18 17 2 1 b17 lsb msb-justified format w s left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 b2 > = 8 > = 8 b ck d ata fig.13 serial interface input and output formats.
2004 apr 22 22 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 9.1 introduction the exchange of data and control information between the microcontroller and the uda1380, is accomplished through a serial hardware interface comprising the following pins: l3data/sda: microcontroller interface data line l3mode: microcontroller interface mode line l3clock/scl: microcontroller interface clock line. information transfer via the microcontroller bus is organized lsb first, and in accordance with the so called ?l3? format, in which two different modes of operation can be distinguished: address mode and data transfer mode. inside the microcontroller interface there is a hand-shake mechanism which takes care of proper data transfer from the microcontroller interface clock to the destination clock domains. this means that when data is sent to the microcontroller interface, the system clock must be running. 9.2 device addressing the device addressing mode is used to select a device for subsequent data transfer. the address mode is characterized by the signal on pin l3mode being low and a burst of 8 pulses on pin l3clock/scl, accompanied by an 8 bit device address on pin l3data/sda. the fundamental timing is shown in figs 14 and 15. table 6 selection of data transfer table 6 shows that there are two types of data transfers: data and status which can be read and written. table 6 also shows that the data and status read and write actions are combined. the device address consists of one byte, which is split-up in two parts: ? bits 7 to 2 represent a 6-bit device address. in the uda1380 this is 000001 ? bits 1 to 0 called data operation mode, or dom bits, represent the type of data transfer according to table 6. 9.3 slave address the uda1380 acts as a slave receiver or a slave transmitter. therefore the signals l3clock and l3mode are only input signals. the data signal l3data is a bidirectional line. the uda1380 slave address is shown in table 7. table 7 l3 slave address 9.4 register addressing after sending the device address, including the flags (the dom bits) whether information is read or written, one byte is sent with the destination register address using 7 bits, and one bit which signals whet her information will be read or written. the fundamental timing for l3 is given in fig.19. basically there are three forms for register addressing: ? register addressing for l3 write: the first bit is a logic 0 indicating a write action to the destination register, followed by seven register address bits ? prepare read addressing: the first bit of the byte is logic 1; signalling data will be read from the register indicated ? the read action itself: in th is case the device returns a register address prior to sending data from that register. when the first bit of the byte is logic 0, the register address was valid, in case the first bit is a logic 1 the register address was invalid. remarks : ? each time a new destination address needs to be written, the device address must be sent again ? when addressing the device for the first time after power-up of the device, at least one l3 clock-cycle must be given to enable the l3 interface. dom bit 1 dom bit 0 transfer 0 0 not used 0 1 not used 1 0 data and status write or pre-read 1 1 data and status read (msb) bit (lsb) 000001
2004 apr 22 23 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 9.5 data write mode for writing data to a device, four bytes must be sent. figure 14 explains the data write mode in a signal diagram: ? one byte with the device address, being ?00000110?, which is including the lsb code 01 for signalling write to the device ? one byte starting with a logic 0 fo r signalling write, followe d by 7 bits indicating the destinat ion address ? two data bytes. the sysclk signal must be a pplied in data write mode. table 8 l3 write data notes 1. first bit in time. 2. last bit in time. l3 mode data type bit 0 (1) 1234567 (2) addressing modedevice address01100000 data transfer 1 register address 0 a6 a5 a4 a3 a2 a1 a0 data transfer 2 ms data byte d15 d14 d13 d12 d11 d10 d9 d8 data transfer 3 ls data byte d7 d6 d5 d4 d3 d2 d1 d0 9.6 data read mode for reading from the device, first a prepare-read must be done. after this, the device address is sent again. the device then returns with the register address, indicating whether the address was valid or not, and the data of the register. the following five steps explain this procedure, and an example of transmission is given in fig.15. ? one byte with the device address, being ?00000110?, which is including the lsb cod e 01 for signalling write to the device ? one byte is sent with the register address from which it needs to be read. this byte starts with a logic 1, which indicates that there will be a read action from the register ? one byte with the device address including ?11? is sent to the device, being 00000111. the ?11? indicates that the device must write data to the microcontroller, then the microcontroller frees the l3data-bus so the uda1380 can send the register address byte and its two-byte contents ? the device now writes the requested register address on the bus, indicating whether the requested register was valid or not (logic 0 means valid, logic 1 means invalid) ? the device writes the data from the requested register on the bus, being two bytes. the sysclk signal must be applied in data read mode.
2004 apr 22 24 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 9 l3 prepare read data notes 1. first bit in time. 2. last bit in time. table 10 l3 read data notes 1. first bit in time. 2. last bit in time. 3. data transfer fr om the uda1380 to the microcontroller. l3 mode data type bit 0 (1) 1234567 (2) addressing mode device address 0 1 1 0 0 0 0 0 data transfer 1 register address 1 a6 a5 a4 a3 a2 a1 a0 l3 mode data type bit 0 (1) 1234567 (2) addressing mode device address 1 1 1 0 0 0 0 0 data transfer 1; note 3 register address 0: valid 1: invalid a6 a5 a4 a3 a2 a1 a0 data transfer 2; note 3 ms data byte d15 d14 d13 d12 d11 d10 d9 d8 data transfer 3; note 3 ls data byte d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 22 25 nxp semiconductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 mgu53 5 l 3clock l3mode l3data 0 write device address dom bits register address data byte 1 data byte 2 10 fig.14 data write mode for l3 version 2. mgu53 6 l 3clock l 3mode l 3data 0 read valid/non-valid device address prepare read send by the device dom bits register address device address register address data byte 1 data byte 2 111 0/1 1 fig.15 data read mode for l3 version 2.
2004 apr 22 26 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 10 i 2 c-bus interface description the uda1380 supports i 2 c-bus microcontroller interface mode as well as the l3-bus mode; all features can be controlled by the microcontroller with the same register addresses as in the l3-bus mode. the exchange of data and control information between the microcontroller and the uda1380 in i 2 c-bus mode is accomplished through a serial hardware interface comprising the following pins: l3clock/scl: microcontroller interface clock line, scl l3mode: sets the bit a1of the i 2 c-bus device address l3data/sda: microcontroller interface data line, sda. figure 20 shows the clock and data timing of the i 2 c-bus transfer. 10.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with the first by te transmitted after the start procedure. the uda1380 device address is [a6 to a0] 00110(a1)0, with bit a1 as the address selection bit (two addresses possible). 10.1.1 d evice address ( pin a1) the uda1380 acts as either a slave receiver or a slave transmitter. therefore the clock signal scl is only an input signal. the data signal sda is a bidirectional line. table 11 shows the device address of the uda1380. the device can be set to one of the two addresses by using bit a1 (which is pin l3mode) to select. table 11 i 2 c-bus device address 10.1.2 r egister address table 12 shows the register address format of the uda1380. the register mapping in i 2 c-bus mode is the same as for the l3-bus interface. table 12 i 2 c-bus register address (msb) bit (lsb) 0 0 1 1 0a10 r/w (msb) bit (lsb) 0 a6 a5 a4a3a2a1 a0
2004 apr 22 27 nxp semiconductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 10.2 write cycle table 13 shows the i 2 c-bus configuration for a write cycle. the write cycle is used to write the data to the internal registers. the device and regi ster addresses are one byte each, the setting data is always a pair of two bytes. the format of the write cycle is as follows: 1. the microcontroller begins by asserting a start condition (s). 2. the first byte (8 bits) contains the device address ?00110a 1 0? and the r/w bit is set to logic 0 (write). 3. the uda1380 asserts an acknowledge (a). 4. the microcontr oller writes the 8-bit address (a ddr) of the uda1380 register to which the data will be written. 5. the uda1380 acknowledges this register address (a). 6. the microcontroller sends two bytes of data with the most significant (ms) byte first, followed by the least significant (ls) byte; after each byte the uda1380 asserts an acknowledge (a). 7. after each pair of bytes transmitted, the register address is auto-incremented; after each byte the uda1380 asserts an acknow ledge (a). 8. the uda1380 frees the i 2 c-bus allowing the microcontroller to generate a stop condition (p). table 13 master transmitter writes to uda1380 registers in the i 2 c-bus mode initial byte acknowledge from uda1380 star t device address r/w register address ms data byte ls data byte stop s 00110a 1 0 0 a addr a ms1 a ls1 a ... a ... a msn a lsn a p auto increment if repeated n groups of 2 bytes are transmitted
2004 apr 22 28 nxp semiconductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 10.3 read cycle table 14 shows the i 2 c-bus configuration for a read cycle. the read cycle is used to read the data values from the internal registers. the format of the read cycle is as follows: 1. the microcontroller begins by asserting a start condition (s). 2. the first byte (8 bits) contains the device address ?00110a 1 0? and the r/w bit is set to logic 0 (write). 3. the uda1380 asserts an acknowledge (a). 4. the microcontr oller writes the 8-bit address (a ddr) of the uda1380 register fr om which the da ta will be read. 5. the uda1380 acknowledges this register address (a). 6. the microcontroller generates a repeated start (sr). 7. the microcontroller generates the device address ?00110a 1 0? again, but this time the r/w bit is set to logic 1 (read). 8. the uda1380 asserts an acknowledge (a). 9. the uda1380 sends two bytes of data with the most significant (ms) byte first, followed by the least significant (ls) byte; a fter each byte the microcontroller asserts an acknowledge (a). 10. after each pair of bytes transmitted, the register address is auto-incremented; after each byte the microcontroller asserts an acknowledge (a). 11. the microcontroller stops this cycle by generating a negative acknowledge (na). 12. the uda1380 frees the i2c-bus allowing the microcontroller to generate a stop condition (p). table 14 master transmitter reads from the uda1380 registers in the i 2 c-bus mode initial byte acknowledge from uda138 0 acknowledge from microcontroller device address r/w register address r/w ms data byte ls data byte s 00110a 1 0 0 a addr a sr 00110a 1 0 1 a ms1 a ls1 a ... a ... a msn a lsn na p auto increment if repeated n groups of 2 bytes are transmitted
2004 apr 22 29 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11 register mapping table 15 register map of control settings (write) table 16 register map of status bits (read-out) register address function system settings (running at the l3-bus or i 2 c-bus clock itself) 00h evaluation modes, wspll settings, clock divider and clock selectors 01h i 2 s-bus i/o settings 02h power control settings 03h analog mixer settings 04h headphone amplifier settings interpolation filter (running at 128f s interpolator clock) 10h master volume control 11h mixer volume control 12h mode selection, left and right bass boost, and treble settings 13h master mute, channel 1 and channel 2 de-emphasis and channel mute 14h mixer, silence detector and interpolation filter oversampling settings decimator (running at 128f s decimator clock) 20h decimator volume control 21h pga settings and mute 22h adc settings 23h agc settings software reset 7fh restore l3-default values register address function headphone driver and interpolation filter 18h interpolation filter status decimator 28h decimator status
2004 apr 22 30 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.1 evaluation modes and clock settings table 17 register address 00h table 18 description of register bits bit151413121110 9 8 symbol ev2 ev1 ev0 ? en_adc en_dec en_dac en_int default00000101 bit76543210 symbol ?? adc_clk dac_clk sys_div1 sys_div0 pll1 pll0 default00000010 bit symbol description 15 to 13 ev[2:0] evaluation bits. bits ev2, ev1 and ev0 are sp ecial control bits for manufacturer?s evaluation and must always be kept at their default values for normal operation of uda1380; default value 000. 12 ? default value 0 11 en_adc adc clock enable. a 1-bit value to enable th e system clock (from sysclk input) to the analog part of the adc. see fig.5 for more detailed information. when this bit is logic 0: clock to adc disabled and when this bit is logic 1: clock to adc running. default value 0. 10 en_dec decimator clock enable. a 1-bit value to enable the 128f s clock to the decimator, the 128f s part of the i 2 s-bus output block and the clock to the adc l3-bus or i 2 c-bus registers. see fig.5 for more detailed information. when this bit is logic 0: clock to the decima tor disabled. when this bit is logic 1: clock to the decimator running. default value 1. 9 en_dac fsdac clock enable. a 1-bit value to enable the 256f s clock to the analog part of the fsdac. see fig.5 for more detailed information. when this bit is logic 0: clock to fsdac disabled. when th is bit is logic 1: clock to the fsdac running. default value 0. 8en_int interpolator clock enable. a 1-bit value to enable the 128f s clock to the interpolator, the 128f s part of the i 2 s-bus input block and the interpolator registers of the l3-bus or i 2 c-bus interface. see fig .5 for more detailed information. when this bit is logic 0: clock to the interpolator disabled. when this bit is logic 1: clock to the in terpolator running. default value 1. 7and6 ? default value 00 5 adc_clk adc clock select. a 1-bit value to select the 128f s clock and the clock of the analog part for the decimator and the adc. this can either be the clock derived from the sysclk input or from the wspll. when th is bit is logic 0: sysclk is used. when this bit is lo gic 1: wspll is used. default value 0.
2004 apr 22 31 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 19 dividers for system clock input table 20 wspll settings 4 dac_clk dac clock select. a 1-bit value to select the clocks for the dac (interpolator and fsdac analog block). in both cases the clocks must be 128f s and 256f s (for the analog part), but in one case the clock is derived from the wsi clock, and in the other case the clock is derived from the sysclk. when this bit is logic 0: sysclk is used . when this bit is logic 1: wspll is used. default value 0. 3 and 2 sys_div[1:0] dividers for system clock input. a 2-bit value to select the proper division factor for the sysclk input in such a way that a128f s clock will be generated from the sysclk clock signal. the 128f s clock is needed for clocking the decimator and interpolator. default value 00, see table 19. 1 and 0 pll[1:0] wspll setting. a 2-bit value to select the wspll input frequency range. these set the proper divider setting for the wspll. the input is the wsi signal, the output inside the ic is a 128f s and a 256f s clock. default value 10, see table 20. sys_div1 sys_div0 input clock on pin sysclk 0 0 256f s (default) 0 1 384f s 1 0 512f s 1 1 768f s pll1 pll0 input frequency range (khz) on pin wsi 0 0 6.25 to 12.5 0 1 12.5 to 25 1 0 25 to 50 (default) 11 50to100 bit symbol description
2004 apr 22 32 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.2 i 2 s-bus input and output settings table 21 register address 01h table 22 description of register bits table 23 digital data input formats bit151413121110 9 8 symbol ????? sfori2 sfori1 sfori0 default00000000 bit76543210 symbol ? sel_ source ? sim ? sforo2 sforo1 sforo0 default00000000 bit symbol description 15 to 11 ? default value 00000 10 to 8 sfori[2:0] digital data input formats. a 3-bit va lue to select the digital input data format (datai input). default value 000, see table 23. 7 ? default value 0 6sel_source digital output interface mode settings. a 1-bit value sel_source to set the mode of the digital output interface source to either the decimator output or the digital mixer output. when this bit is logic 0: source digital output interface mode set to decimator. when this bit is logic 1: source digital output interface mode set to digital mixer output. default value 0. 5 ? default value 0 4sim digital output interface mode settings. a 1-bit value sim sets the mode of the digital output interface. the speed of the bcko pad, being 64f s or 48f s , is selected by the bits sys_div[1:0]. in case the 384f s or 768f s mode is selected the output clock is 48f s , in case 256f s or 512f s is selected, the bcko is 64f s . when this bit is logic 0: mode of digital output interface is set to slave. when this bit is logic 1: mode of digital outp ut interface is set to master. default value 0. 3 ? default value 0 2 to 0 sforo[2:0] digital data output formats. a 3-bit value to set the digital data output format (on pin datao). default value 000, see table 24. sfori2 sfori1 sfori0 serial_format_dai 000 i 2 s-bus (default) 0 0 1 lsb-justified, 16 bits 0 1 0 lsb-justified, 18 bits 0 1 1 lsb-justified, 20 bits 1 0 1 msb-justified 1 0 0 not used: mapped to i 2 s-bus 110 111
2004 apr 22 33 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 24 digital data output formats 11.3 power control settings 11.3.1 p ower control setting bias circuits using a 1-bit value, the power control settings of the bias circuits of the adc, avc and fsdac can be set. when this bit is set to logic 0, the complete bias circuits of the analog front-end and the fsdac are shut down. in this case, the reference voltage disappears from the input of the adcs an d lna and the output of the fsdac, this can cause plops but saves power. table 25 register address 02h table 26 description of register bits sforo2 sforo1 sforo0 serial_format_dao 000 i 2 s-bus (default) 0 0 1 lsb-justified, 16 bits 0 1 0 lsb-justified, 18 bits 0 1 1 lsb-justified, 20 bits 1 0 0 lsb-justified, 24 bits 1 0 1 msb-justified 1 1 0 not used: mapped to i 2 s-bus 111 bit151413121110 9 8 symbol pon_pll ? pon_hp ?? pon_dac ? pon_ bias default00000000 bit76543210 symbol en_avc pon_avc ? pon_lna pon_ pgal pon_ adcl pon_ pgar pon_ adcr default00000000 bit symbol description 15 pon_pll power-on wspll. when this bit is logic 0: power-off; when this bit is logic 1: power-on. default value 0. 14 ? default value 0 13 pon_hp power-on headphone driver. a 1-bit value to switch the headphone driver into power-on or power-down mode. when this bit is logic 0: headphone driver is powered-off; when this bit is logic 1: headphone driver is powered-on. default value 0. 12 and 11 ? default value 00 10 pon_dac power-on dac. a 1-bit value to switch the dac into power-on or power-down mode. in this power-down mode the v ref (half the power supply voltage) will remain on the fsdac outp ut. when this bit is logic 0: dac is powered-off; when this bit is logic 1: dac is powered-on. default value 0. 9 ? default value 0
2004 apr 22 34 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 8pon_bias power-on bias. a 1-bit value to set the power control setting of the adc, avc and fsdac. when this bit is logic 0: adc, avc and fsdac bias circuits are powered-off; when this bit is logic 1: power-on bias for adc, avc and fsdac. default value 0. 7en_avc enable control avc. a 1-bit value to enable or disable the analog mixer. when this bit is logic 0: analog mixer is disabled; when this bit is logic 1: analog mixer is enabled. default value 0. 6pon_avc power-on avc. a 1-bit value to have power-on control for the analog mixer. when this bit is logic 0: analog mixer powered-off; when this bit is logic 1: analog mixer powered-on. default value 0. 5 ? default value 0 4pon_lna power-on lna. a 1-bit value to power-on the lna and sdc. when this bit is logic 0: lna and sdc are powered-off; when this bit is logic 1: lna and sdc are powered-on. default value 0. 3pon_pgal power-on pgal. a 1-bit value to have power-on control for the pga left. when this bit is logic 0: left pga is powe red-off; when this bit is logic 1: left pga is powered-on. default value 0. 2pon_adcl power-on adcl. a 1-bit value to have power-on control for the adc left. when this bit is logic 0: left adc is pow ered-off; when this bit is logic 1: left adc is powered-on. default value 0. 1pon_pgar power-on pgar. a 1-bit value to have power-on control for the pga right. when this bit is logic 0: right pga is po wered-off; when this bit is logic 1: right pga is powered-on. default value 0. 0pon_adcr power-on adcr. a 1-bit value to have power-on control for the adc right. when this bit is logic 0: right adc is po wered-off; when this bit is logic 1: right adc is powered-on. default value 0. bit symbol description
2004 apr 22 35 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.4 analog mixer settings table 27 register address 03h table 28 description of register bits bit151413121110 9 8 symbol ?? avcl5 avcl4 avcl3 avcl2 avcl1 avcl0 default00111111 bit76543210 symbol ?? avcr5 avcr4 avcr3 avcr2 avcr1 avcr0 default00111111 bit symbol description 15 and 14 ? default value 00 13 to 8 avcl[5:0] analog volume control. a 6-bit value to program the left master volume attenuation. the range is from +16.5 to ? 48 and ? db in steps of 1.5 db. the 16.5 db gain is there to boost the 150 mv (rms) which comes from for instance an fm tuner ic to 1 v (rms) needed to drive the headphone driver full-swing. default value 111111, see table 29. 7and6 ? default value 00 5 to 0 avcr[5:0] analog volume control. a 6-bit value to program the right master volume attenuation. the range is from +16.5 to ? 48 and ? db in steps of 1.5 db. the 16.5 db gain is there to boost the 150 mv (rms) which comes from for instance an fm tuner ic to 1 v (rms) needed to drive the headphone driver full-swing. default value 111111, see table 29.
2004 apr 22 36 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 29 analog volume control 11.5 headphone amplifier settings using a 1-bit value, it is possible to disable the short-circ uit protection of the headphone amplifier. this function is provided to offer maximum freedom to users, however due to the nature of this function there is the drawback of possible damage. bits rsv12, rsv11, rsv10, rsv02, rsv01, and rsv00 are special control bits for manufacturer?s evaluation and must always be kept at their default values for normal operation of uda1380. table 30 register address 04h table 31 description of register bits avcl5 avcr5 avcl4 avcr4 avcl3 avcr3 avcl2 avcr2 avcl1 avcr1 avcl0 avcr0 volume (db) 000000 16.5 000001 15 000010 13.5 000011 12 000100 10.5 :::::: : 101011 ? 48 101100 ? :::::: : 111111 ? (default) bit151413121110 9 8 symbol ????? rsv12 rsv11 rsv10 default ????? 010 bit76543210 symbol ????? rsv02 en_scp rsv00 default ????? 010 bit symbol description 15 to 11 ? not used 10 rsv12 reserved bit. default value 0 9 rsv11 reserved bit. default value 1 8 rsv10 reserved bit. default value 0 7to3 ? not used 2 rsv02 reserved bit. default value 0 1 en_scp short circuit protection enable. a 1-bit value to enable the short circuit protection of the headphone amplifier. when this bit is set to logic 0: short-circuit protection is disabled. when this bit is set to logic 1: short-circ uit protection is enabled. default value 1. short-circuit detection is always enabled regardless of this bit. 0 rsv00 reserved bit. default value 0
2004 apr 22 37 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.6 master volume control table 32 register address 10h table 33 description of register bits table 34 master volume control bits bit151413121110 9 8 symbol mvcr_7 mvcr_6 mvcr_5 mvcr_ 4 mvcr_3 mvcr_2 mvcr_1 mvcr_0 default00000000 bit76543210 symbol mvcl_7 mvcl_6 mvcl_5 mvcl _4 mvcl_3 mvcl_2 mvcl_1 mvcl_0 default00000000 bit symbol description 15 to 8 mvcr_[7:0] master volume control right. an 8-bit value to program the right channel volume attenuation. the range is from 0 to ? 78 db and ? db in steps of 0.25 db. default value 00000000, see table 34. 7 to 0 mvcl_[7:0] master volume control left. an 8-bit value to program the left channel volume attenuation. the range is from 0 to ? 78 db and ? db in steps of 0.25 db. default value 00000000, see table 34. mvcr_7 mvcl_7 mvcr_6 mvcl_6 mvcr_5 mvcl_5 mvcr_4 mvcl_4 mvcr_3 mvcl_3 mvcr_2 mvcl_2 mvcr_1 mvcl_1 mvcr_0 mvcl_0 volume (db) 00000000 0(default) 00000001 ? 0.25 00000010 ? 0.50 00000011 ? 0.75 00000100 ? 1 :::::::: : 11001000 ? 50 11001100 ? 51 11001101 ? 51.25 11001110 ? 51.50 11001111 ? 51.75 11010000 ? 52 11010100 ? 54 11011000 ? 56 :::::::: : 11101100 ? 66 11110000 ? 69 11110100 ? 72 11111000 ? 78 11111100 ?
2004 apr 22 38 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.7 mixer volume control table 35 register address 11h table 36 description of register bits table 37 digital mixer volume control bit151413121110 9 8 symbol vc2_7 vc2_6 vc2_5 vc2_4 vc2_3 vc2_2 vc2_1 vc2_0 default11111111 bit76543210 symbol vc1_7 vc1_6 vc1_5 vc1_4 vc1_3 vc1_2 vc1_1 vc1_0 default00000000 bit symbol description 15 to 8 vc2_[7:0] digital mixer volume control. an 8-bit value to program the channel 2 volume attenuation. the range is 0 to ? 72 db and ? db in steps of 0.25 db. default value for channel 2 is 11111111, see table 37. 7to0 vc1_[7:0] digital mixer volume control. an 8-bit value to program the channel 1 volume attenuation. the range is 0 to ? 72 db and ? db in steps of 0.25 db. default value for channel 1 is 00000000, see table 37. vc2_7 vc1_7 vc2_6 vc1_6 vc2_5 vc1_5 vc2_4 vc1_4 vc2_3 vc1_3 vc2_2 vc1_2 vc2_1 vc1_1 vc2_0 vc1_0 volume (db) 000000000 00000001 ? 0.25 00000010 ? 0.50 00000011 ? 0.75 00000100 ? 1 ::::::::: 10110100 ? 45 10110101 ? 45.25 10110110 ? 45.50 10110111 ? 45.75 10111000 ? 46 10111100 ? 48 11000000 ? 50 ::::::::: 11010100 ? 60 11011000 ? 63 11011100 ? 66 11100000 ? 72
2004 apr 22 39 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.8 mode, bass boost and treble table 38 register address 12h table 39 description of register bits table 40 flat/minimum/maximum setting bits 11100100 ? ::::::::: 11111100 ? bit151413121110 9 8 symbol m1 m0 trl1 trl0 bbl3 bbl2 bbl1 bbl0 default00000000 bit76543210 symbol ?? trr1 trr0 bbr3 bbr2 bbr1 bbr0 default00000000 bit symbol description 15 and 14 m[1:0] flat/minimum/maximum setting. a 2-bit value to program the mode of the sound processing filters of bass boost and treble. default value 00, see table 40. 13 and 12 trl[1:0] treble setting left. a 2-bit value to program the mode of the sound processing filter of treble. the used setting depends on the bits m1 and m0. default value 00, see table 41. 11 to 8 bbl[3:0] bass boost setting left. a 4-bit value to program the bass boost setting, which can be set for left and right independently. the used set depends on the bits m1 and m0. default value 0000, see table 42. 7 and 6 ? default value 00 5 and 4 trr[1:0] treble setting right. a 2-bit value to program the mode of the sound processing filter of treble. default value 00, see table 41. 3to0 bbr[3:0] bass boost sett ing right. a 4-bit value to program the bass boost setting, which can be set for left and right independently. the used set depends on the mode bits. default value 0000, see table 42. m1 m0 mode 0 0 flat (default) 0 1 minimum 1 0 minimum 1 1 maximum vc2_7 vc1_7 vc2_6 vc1_6 vc2_5 vc1_5 vc2_4 vc1_4 vc2_3 vc1_3 vc2_2 vc1_2 vc2_1 vc1_1 vc2_0 vc1_0 volume (db)
2004 apr 22 40 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 41 treble setting bits table 42 bass boost setting bits trl1 trr1 trl0 trr0 flat set (db) minimum set (db) maximum set (db) 0 0 0 (default) 0 (default) 0 (default) 0 1 022 1 0 044 1 1 066 bbl3 bbr3 bbl2 bbr2 bbl1 bbr1 bbl0 bbr0 flat set (db) minimum set (db) maximum set (db) 00000(default)0(default)0(default) 0001022 0010044 0011066 0100088 010101010 011001212 011101414 100001616 100101818 101001820 101101822 110001824 110101824 111001824 111101824
2004 apr 22 41 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.9 master mute, channel de-emphasis and mute table 43 register address 13h table 44 description of register bits table 45 de-emphasis selection bits bit151413121110 9 8 symbol ? mtm ?? mt2 de2_2 de2_1 de2_0 default01001000 bit76543210 symbol ???? mt1 de1_2 de1_1 de1_0 default00000000 bit symbol description 15 ? default value 0 14 mtm master mute. a 1-bit value to enable the digital mute for the master. when this bit is logic 0: no soft mute of master . when this bit is logic 1: soft mute of master. default value 1. 13 and 12 ? default value 00 11 mt2 channel 2 mute. a 1-bit value to enable the digital mute for channel 2. after enabling the mixer, bit mt2 must be set to logic 0. when this bit is logic 0: no soft mute of channel 2. when this bit is logic 1: soft mute of channel 2. default value 1 (meaning that channel 2 is always muted, even when the mixer is enabled). 10 to 8 de2_[2:0] de-emphasis. a 3-bit value to enable the digital de-emphasis filter for channel 2. default value 000, see table 45. 7to4 ? default value 0000 3mt1 channel 1 mute. a 1-bit value to enable the di gital mute for channel 1. when this bit is logic 0: no soft mute of channel 1. when this bit is logic 1: soft mute of channel 1. default value 0. 2to0 de1_[2:0] de-emphasis. a 3-bit value to enable the digital de-emphasis filter for channel 1. default value 000, see table 45. de2_2 de1_2 de2_1 de1_1 de2_0 de1_0 function 0 0 0 off (default) 001 32khz 010 44.1khz 011 48khz 100 96khz
2004 apr 22 42 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.10 mixer, silence detect or and oversampling settings table 46 register address 14h table 47 description of register bits bit 15 14 13 12 11 10 9 8 symbol da_pol_inv sel_ns mix_pos mix ???? default 0 0 0 0 0000 bit 7 6 5 4 3210 symbol silence sdet_on sd_value1 sd_value0 ?? os1 os0 default 0 0 0 0 0000 bit symbol description 15 da_pol_inv dac polarity control. a 1-bit value to control the signal polarity of the dac output signal. when this bit is logic 0: dac output not inverted. when this bit is logic 1: dac output inverted. default value 0. 14 sel_ns noise shaper order select. a 1-bit value to select between the 3rd-order and the 5th-order noise shaper. when this bit is logic 0: select 3rd-order noise shaper. when this bit is logic 1: select 5th-order noise shaper. default value 0. 13 mix_pos mixer signal control. a 2-bit value to select the digital mixer settings inside the interpolation filter. defaul t value 0. by default the mixer is off, see table 48. 12 mix 11 to 8 ? default value 0000 7silence silence mode. a 1-bit value to force the da c output to silence. when this bit is logic 0: no overruling. the setting of the fsdac silence switch depends on the status of the digital silence detector circuit and the master_mute status. when this bit is logic 1: overruling. the fsdac silence switch is activated, independent of the status of the digital silence detector circuit or the master_mute status. default value 0. 6sdet_on silence detector enable. a 1-bit value to enable the digital silence detector. when this bit is logic 0: silence detection circuit disabled. when this bit is logic 1: silence detection circuit enabled. default value 0. 5 and 4 sd_value[1:0] silence detect or settings. a 2-bit value to program the silence detector, the number of ?zero? samples counted before the silence detector signals whether there has been digital silence. default value 00, see table 49. 3 and 2 ? default value 00 1 and 0 os[1:0] oversampling input settings. a 2-bit value to select the oversampling input mode. default va lue 00, see table 50.
2004 apr 22 43 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 48 mixer signal control setting bits table 49 silence detector setting bits table 50 oversampling input setting bits 11.11 decimator volume control table 51 register address 20h table 52 description of register bits mix_pos mix function 0 0 no mixing; default 1 0 volume of channel 1 is forced to 0 db and volume of channel 2 is forced to ? db 0 1 mixing is done before the sound processing: input signals are automatically scaled by 6 db in order to prevent clipping during adding; after the addition, the 6 db scaling is compensated 1 1 mixing is done after the sound processing: input signals are automatically scaled in order to prevent clipping during adding sd_value1 sd_value0 function 0 0 3200 samples; default 0 1 4800 samples 1 0 9600 samples 1 1 19200 samples os1 os0 function 0 0 single-speed input is normal input; mixing possible; default 0 1 double-speed input is after first half-band; no mixing possible 1 0 quad-speed input is in front of noise shaper; no mixing possible 1 1 reserved bit 151413121110 9 8 symbol ml_dec7 ml_dec6 ml_dec5 ml_dec4 ml_dec3 ml_dec2 ml_dec1 ml_dec0 default 00000000 bit76543210 symbol mr_dec7 mr_dec6 mr_dec5 mr_dec4 mr_dec3 mr_dec2 mr_dec1 mr_dec0 default 00000000 bit symbol description 15 to 8 ml_dec[7:0] adc volume control left. an 8-bit value to program the gain of the decimator for left and right independently. the ranges are +24 to ? 63.5 db and ? db in steps of 0.5 db. the default setting is 0 db (value 00000000), see table 53. 7to0 mr_dec[7:0] adc volume control right. an 8-bit value to program the gain of the decimator for left and right independently. the ranges are +24 to ? 63.5 db and ? db in steps of 0.5 db. the default setting is 0 db (value 00000000), see table 53.
2004 apr 22 44 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 53 adc volume control setting bits 11.12 pga settings and mute table 54 register address 21h table 55 description of register bits ml_dec7 mr_dec7 ml_dec6 mr_dec6 ml_dec5 mr_dec5 ml_dec4 mr_dec4 ml_dec3 mr_dec3 ml_dec2 mr_dec2 ml_dec1 mr_dec1 ml_dec0 mr_dec0 gain (db) 00110000 24 0010111123.5 00101110 23 :::::::: : 00000010 1 00000001 0.5 000000000 (default) 11111111 ? 0.5 :::::::: : 10000100 ? 62 10000011 ? 62.5 10000010 ? 63 10000001 ? 63.5 10000000 ? bit 15 141312 11 10 9 8 symbol mt_adc ??? pga_gain ctrlr3 pga_gain ctrlr2 pga_gain ctrlr1 pga_gain ctrlr0 default10000000 bit76543210 symbol ? ??? pga_gain ctrll3 pga_gain ctrll2 pga_gain ctrll1 pga_gain ctrll0 default00000000 bit symbol description 15 mt_adc decimator mute. a 1-bit value to enable the digital linear mute. when this bit is logic 0: no muting. when this bit is logic 1: muting. default value 1. 14 to 12 ? default value 000
2004 apr 22 45 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 56 adc input amplifier pga gain setting bits 11.13 adc settings table 57 register address 22h table 58 description of register bits 11 to 8 pga_gain ctrlr[3:0] adc input amplifier right gain settings. a 4-bit value to prog ram the gain of the input amplifier. there are nine settings, for a gain range from 0 to 24 db in steps of 3 db. the gain control of the pga is independent for left and right. default value 0000, see table 56. 7to4 ? default value 0 3to0 pga_gain ctrll[3:0] adc input amplifier le ft gain settings. a 4-bit value to program the gain of the input amplifier. there are nine settings, for a gain range from 0 to 24 db in steps of 3 db. the gain control of the pga is independent for left and right. default value 0000, see table 56. pga_gainctrlr3 pga_gainctrll3 pga_gainctrlr2 pga_gainctrll2 pga_gainctrlr1 pga_gainctrll1 pga_gainctrlr0 pga_gainctrll0 pga_gain (db) 00000 (default) 00013 00106 00119 010012 010115 011018 011121 1xxx24 bit 15 14 13 12 11 10 9 8 symbol ??? adcpol_ inv vga_ctrl3 vga_ ctrl2 vga_ctrl1 vga_ctrl0 default 0 0 0 0 0 0 0 0 bit 765 4 3 2 1 0 symbol ??? ? sel_lna sel_mic skip_dcfil en_dcfil default 0 0 0 0 0 0 1 0 bit symbol description 15 to 13 ? default value 000 12 adcpol_inv adc polarity control. a 1-bit value to sele ct adc polarity. when this bit is logic 0: polarity of adc non-inverting. when this bit is logic 1: polarity of adc inverting. default value 0. 11 to 8 vga_ctrl[3:0] microphone input vga gain settings. a 4-bit value to program the gain of the lna in the microphone input channel. the range is 0 to 30 db in steps of 2 db. default value 0000, see table 59. bit symbol description
2004 apr 22 46 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 59 microphone input vga gain setting bits 7to4 ? default value 0000 3sel_lna line input select. a 1-bit value to set the multiplexer in the analog front-end to select between the lna or the enable-in input for the left adc. when this bit is logic 0: select line input. when this bit is logic 1: select lna for the left adc. default value 0. 2sel_mic microphone input select. a 1-bit value to set the multiplexer at the adc right channel output (on bit-stream level) which selects either the right channel data or the left channel data. in case only the microphone input is used, the microphone signal can be applied to the decimator for both left and right. when this bit is logic 0: select right channel adc. when this bit is logic 1: select left channel a dc (for instance for microphone input). default value 0. 1skip_dcfil dc filter bypass. a 1-bit value set to skip the dc filter which is just before the decimator. this dc filter is there to compensate for the dc offset added in the adc (to remove idle tones from the audio band). this dc signal added (the dc dither) must not be amplified in order to prevent clipping. therefore this dc offset is removed first. when this bit is logic 0: dc f ilter enabled. when this bit is logic 1: dc filter bypassed. default value 1. 0 en_dcfil dc filter enable. a 1-bit value set to enable the dc filter which is at the output of the decimator (running at 1f s ). when this bit is logic 0: dc f ilter disabled. when this bit is logic 1: dc filter enabled. default value 0. vga_ctrl3 vga_ctrl2 vga_ctrl 1 vga_ctrl0 lna gain (db) 00000(default) 00012 00104 00116 01008 010110 011012 011114 100016 100118 101020 101122 110024 110126 111028 111130 bit symbol description
2004 apr 22 47 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.14 agc settings table 60 register address 23h table 61 description of register bits table 62 agc time constant setting bits bit15141312 11 10 9 8 symbol ???? ? agc_time2 agc_time1 agc_time0 default00000000 bit76543210 symbol ???? agc_level1 agc_level0 ? agc_en default00000000 bit symbol description 15 to 11 ? default value 00000. 10 to 8 agc_time[2:0] agc time constant settings. a 3-bit value to set the agc time constants, being the attack and decay time constants. the given constants are for 44.1 and 8 khz sampling frequencies, and must be scaled either down or up according to the sampling frequency used. default value 000, see table 62. 7to4 ? default value 0000 3 and 2 agc_level[1:0] agc target level settings. a 2-bit value to set the agc target level. default value 00, see table 63. 1 ? default value 0 0agc_en agc enable control. a 1-bit value to enable or disable the agc. when the agc is enabled, the bit skip_dcfil must be set to logic 0 to avoid disturbance on the output signal due to the dc offset added in the adc. when this bit is logic 0: agc off, manual gain control via the left and right decimator volume control. when this bit is logic 1: agc enabled, with manual microphone gain setting via vga. default value 0. agc_time2 agc_time1 agc_time0 agc setting 44.1 khz sampling 8 khz sampling attack time (ms) decay time (ms) attack time (ms) decay time (ms) 0 0 0 11 100 61 551 (default) 0 0 1 16 100 88.2 551 0 1 0 11 200 61 1102 0 1 1 16 200 88.2 1102 1 0 0 21 200 116 1102 1 0 1 11 400 61 2205 1 1 0 16 400 88.2 2205 1 1 1 21 400 116 2205
2004 apr 22 48 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 table 63 agc target level setting bits 11.15 restore l3 default values (software reset) table 64 register address 7fh 11.16 headphone driver and inte rpolation filter (read-out) table 65 register address 18h table 66 description of register bits agc_level1 agc_level0 agc t arget level value (dbfs) 00 ? 5.5 (default) 01 ? 8 10 ? 11.5 11 ? 14 bit 1514131211 10 9 8 default value ????? ? ? ? bit 76543 2 1 0 default value ????? ? ? ? bit 1514131211 10 9 8 symbol ????? hp_stctv hp_stctl hp_stctr bit 76543 2 1 0 symbol ? sdetr2 sdetl2 sdetr1 sdetl1 mute_ state_m mute_ state_ch2 mute_ state_ch1 bit symbol description 15 to 11 ? not used 10 hp_stctv headphone driver shor t-circuit detection. when this bit is logic 0: headphone driver is not short-circuit protected. when this bit is logic 1: headphone driver short-circuit protection is activated. 9 hp_stctl left headphone driver short-circuit detection. when this bit is logic 0: left channel headphone driver is not short-circuit protected. when this bit is logic 1: left channel headphone driver short-circuit protection is activated. 8 hp_stctr right headphone driver short-circuit detection. when this bit is logic 0: right channel headphone driver not short-circuit protected. when this bit is logic 1: right channel headphone driver short-circuit protection activated. 7 ? not used 6sdetr2 interpolator silence de tect channel 2 right. when this bit is logic 0: interpolator on channel 2 right input has detected no silence. when this bit is logic 1: interpolator on channel 2 right input has detected silence. 5sdetl2 interpolator silence de tect channel 2 left. when this bit is logic 0: interpolator on channel 2 left input has detected no silence. when this bit is logic 1: interpolator on channel 2 left input has detected silence.
2004 apr 22 49 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 11.17 decimator read-out table 67 register address 28h table 68 description of register bits 4sdetr1 interpolator silence de tect channel 1 right. when this bit is logic 0: interpolator on channel 1 right input has detected no silence. when this bit is logic 1: interpolator on channel 1 right input has detected silence. 3sdetl1 interpolator silence de tect channel 1 left. when this bit is logic 0: interpolator on channel 1 left input has detected no silence. when this bit is logic 1: interpolator on channel 1 left input has detected silence. 2 mute_state_m interpolator muting. a 1-bit value which signals whether the interpolator has reached mute or not. when this bit is logic 0: interpolator is not muted. when this bit is logic 1: interpolator is muted. 1 mute_state_ch2 interpolator muting channel 2. when this bit is logic 0: interpolator channel 2 is not muted. when this bit is logic 1: interpolator channel 2 is muted. 0 mute_state_ch1 interpolator muting channel 1. when this bit is logic 0: interpolator channel 1 is not muted. when this bit is logic 1: interpolator channel 1 is muted. bit 151413 12 11 10 9 8 symbol ???????? bit 765 4 3 2 1 0 symbol ??? agc_stat ? mt_adc_stat ? overflow bit symbol description 15 to 5 ? not used 4agc_stat agc gain status. a 1-bit value which signals whether the agc gain exceeds 8 db or not. only valid when the agc is switched on. when this bit is logic 0: agc gain <8 db. when this bit is logic 1: agc gain 8db. 3 ? not used 2 mt_adc_stat decimator mute. a 1-bit value which signals whether the decimator has reached mute or not. when this bit is logic 0: decimator has not muted. when this bit is logic 1: decimator has muted. 1 ? not used 0 overflow digital output over flow detection. a 1-bit value which signals whether the digital output amplitude exceeds ? 1.16 db or not. when this bit is logic 0: no overflow detected (read-out). when this bit is logic 1: overflow detected (read-out). bit symbol description
2004 apr 22 50 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 12 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. all supply connections must be made to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k series resistor. 3. equivalent to discharging a 200 pf capacitor via a 0.75 h series inductor. 4. dac operation after short-circuiting cannot be warranted. 13 handling inputs and outputs are protected against electrostatic discharg e in normal handling. however, to be totally safe, it is advised to take normal precautions appropriate to handling mos devices. 14 thermal characteristics 15 quality specification in accordance with ?snw-fq-611d? . symbol parameter conditions min. max. unit v dd supply voltage note 1 ? 4v t xtal(max) maximum crystal temperature ? 150 c t stg storage temperature ? 65 +125 c t amb ambient temperature ? 40 +85 c v es electrostatic handling voltage note 2 ? 2000 +2000 v note 3 ? 200 +200 v i lu(prot) latch-up protection current t amb =125 c; v dd =3.6v ? 100 ma i sc(dac) short-circuit current of dac t amb =0 c; v dd = 3 v; note 4 output short-circuited to v ssa(da) ? 450 ma output short-circuited to v dda(da) ? 325 ma symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air tssop32 package 115 k/w hvqfn32 package 35 k/w
2004 apr 22 51 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 16 dc characteristics v ddd =v dda(ad) =v dda(da) =v dda(hp) =3.0v; t amb =25 c; r l =5k ; all voltages measured with respect to ground; unless otherwise specified. symbol parameter conditions min. typ. max. unit supplies; note 1 v dda(ad) adc analog supply voltage 2.4 3.0 3.6 v v dda(da) dac analog supply voltage 2.4 3.0 3.6 v v dda(hp) headphone analog supply voltage note 2 2.4 3.0 3.6 v v ddd digital supply voltage 2.4 3.0 3.6 v i dda(ad) adc analog supply current one adc and microphone amplifier enabled; f s =48khz ? 4.5 ? ma two adcs and pga enabled; f s =48khz ? 7.0 ? ma all adcs and pgas power-down, but avc activated; f s =48khz ? 3.3 ? ma all adcs, pgas and lna power-down; f s =48khz ? 1.0 ? a i dda(da) dac analog supply current operating mode; f s =48khz ? 3.4 ? ma power-down mode; f s =48khz ? 0.1 ? a i dda(hp) headphone analog supply current no signal applied (quiescent current) ? 0.9 ? ma power-down mode ? 0.1 ? a i ddd digital supply current operating mode; f s =48khz ? 10.0 ? ma playback mode; f s =48khz ? 5.0 ? ma record mode; f s =48khz ? 6.0 ? ma power-down mode; f s =48khz ? 1.0 ? a i dd(tot) total supply current playback mode (without headphone); f s =48khz ? 8 ? ma playback mode (with headphone); no signal; f s =48khz ? 9 ? ma record mode (audio); f s =48khz ? 13 ? ma record mode (speech); f s =48khz ? 10 ? ma record mode (audio and speech); f s =48khz ? 13 ? ma fully operating; f s =48khz ? 23 ? ma signal mix-in operating, using fsdac, avc (with headphone); no signal; f s =48khz ? 12 ? ma power-down mode; f s =48khz ? 2 ? a
2004 apr 22 52 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 notes 1. all supply connections must be made to the same power supply unit. 2. when the supply voltages are below 2.7 v and the headphone load impedance is 16 , it is recommended to limit the dac and the headphone output to less than -2 db, otherwise clipping may occur. 3. v dda =v dda(da) =v dda(ad) . 4. when higher capacitive loads must be driven, a 100 resistor must be connected in series with the dac output in order to prevent oscillations in the output operational amplifier. digital input pins (5 v tolerant ttl compatible) v ih high-level input voltage 2.0 ? 5.5 v v il low-level input voltage ? 0.5 ? +0.8 v ? i li ? input leakage current ?? 1 a c i input capacitance ?? 10 pf digital output pins v oh high-level output voltage i oh = ? 2 ma 0.85v ddd ?? v v ol low-level output voltage i ol =2ma ?? 0.4 v reference voltage v ref reference voltage with respect to v ssa(ad) ; note 3 0.45v dda 0.5v dda 0.55v dda v r o(vref) output resistance on pin v ref ? 12.5 ? k analog-to-digital converter v adcp positive reference voltage of the adc ? v dda(ad) ? v v adcn negative reference voltage of the adc ? 0 ? v r i input resistance ? 12 ? k c i input capacitance ? 24 ? pf digital-to-analog converter r l load resistance 3 ?? k c l load capacitance note 4 ?? 50 pf power consumption (supply voltage 3.0 v; f s =48khz) p tot total power dissipation playback mode (without headphone) ? 24 ? mw playback mode (with headphone) ? 27 ? mw record mode (audio) ? 39 ? mw record mode (speech) ? 30 ? mw record mode (audio and speech) ? 40 ? mw full operation ? 69 ? mw power-down mode ? 6 ? w symbol parameter conditions min. typ. max. unit
2004 apr 22 53 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 17 ac characteristics v ddd =v dda(ad) =v dda(da) =v dda(hp) =3.0v; f i =1khz at ? 1db; t amb =25 c; r l =5k ; all voltages measured with respect to ground; unless otherwise specified. symbol parameter conditions min. typ. max. unit analog-to-digital converter d o digital output level 0 db setting; v i(rms) =1.0v ? 1.5 ? 1 ? 0.5 dbfs 3 db setting; v i(rms) = 708 mv ? 1.5 ? 1 ? 0.5 dbfs 6 db setting; v i(rms) = 501 mv ? 1.5 ? 1 ? 0.5 dbfs 9 db setting; v i(rms) = 354 mv ? 1.5 ? 1 ? 0.5 dbfs 12 db setting; v i(rms) =252mv ? 1.5 ? 1 ? 0.5 dbfs 15 db setting; v i(rms) =178mv ? 1.5 ? 1 ? 0.5 dbfs 18 db setting; v i(rms) =125mv ? 1.5 ? 1 ? 0.5 dbfs 21 db setting; v i(rms) =89mv ? 1.5 ? 1 ? 0.5 dbfs 24 db setting; v i(rms) =63mv ? 1.5 ? 1 ? 0.5 dbfs v i unbalance between channels ? <0.1 ? db (thd + n)/s 48 total harmonic distortion-plus-noise to signal at f s =48khz at ? 1dbfs 0db setting ?? 85 ? 80 db 3db setting ?? 85 ? db 6db setting ?? 85 ? db 9db setting ?? 85 ? db 12 db setting ?? 84 ? db 15 db setting ?? 83 ? db 18 db setting ?? 82 ? db 21 db setting ?? 80 ? db 24 db setting ?? 78 ? db at ? 60 dbfs; a-weighted 0db setting ?? 37 ? 32 db 3db setting ?? 36 ? db 6db setting ?? 36 ? db 9db setting ?? 36 ? db 12 db setting ?? 35 ? db 15 db setting ?? 34 ? db 18 db setting ?? 33 ? db 21 db setting ?? 32 ? db 24 db setting ?? 30 ? db s/n 48 signal-to-noise ratio at f s =48khz v i = 0 v; a-weighted 92 97 ? db cs channel separation ? 100 ? db psrr power supply rejection ratio f ripple =1khz; v ripple = 30 mv (p-p) ? 80 ? db
2004 apr 22 54 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 lna input plus analog-to-digital converter v i(rms) input voltage (rms value) at 0 dbfs digital output; 2.2 k source impedance ?? 35 mv (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db ?? 74 ? db at ? 60 db; a-weighted ?? 25 ? db s/n 48 signal-to-noise ratio at f s =48khz v i = 0 v; a-weighted ? 85 ? db cs channel separation ? 70 ? db digital-to-analog converter v o(rms) output voltage (rms value) at 0 dbfs digital input; note 1 ? 0.9 ? v v o unbalance between channels ? <0.1 ? db (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db ?? 85 ? 80 db at ? 60 db; a-weighted ?? 40 ? 35 db (thd+n)/s 96 total harmonic distortion-plus-noise to signal ratio at f s =96khz at 0 db ?? 80 ? 75 db at ? 60 db; a-weighted ?? 37 ? 32 db s/n 48 signal-to-noise ratio at f s =48khz code = 0; a-weighted 95 100 ? db s/n 96 signal-to-noise ratio at f s =96khz code = 0; a-weighted 92 97 ? db cs channel separation ? 90 ? db psrr power supply rejection ratio f ripple =1khz; v ripple = 30 mv (p-p) ? 60 ? db headphone driver p o(rms) output power (rms value) at 0 dbfs digital input, assuming r l =16 30 35 40 mw (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db; r l =16 ; note 2 ?? 60 ? 52 db at 0 db; r l =5k ?? 82 ? 77 db at ? 60 db; a-weighted ?? 33 ? 27 db cs channel separation r l =16 using pin v ref(hp) ; no dc decoupling capacitors; note 3 55 60 ? db r l =16 single-ended application with dc decoupling capacitors (100 f typical) 63 68 ? db r l =32 single-ended application with dc decoupling capacitors (100 f typical) 69 74 ? db s/n 48 signal-to-noise ratio at f s =48khz code = 0; a-weighted 87 93 ? db symbol parameter conditions min. typ. max. unit
2004 apr 22 55 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 notes 1. the output voltage of the dac is proportional to the dac power supply voltage. 2. when the supply voltages are below 2.7 v and the headphone load impedance is 16 , it is recommended to limit the dac and the headphone output to less than -2 db, otherwise clipping may occur. 3. channel separation performance is measured at the ic pin. avc (line input via adc input, output on line output and headphone driver) v i(rms) input voltage (rms value) ? 150 ? mv (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db ?? 80 ? db at ? 60 db; a-weighted ?? 28 ? db s/n 48 signal-to-noise ratio at f s =48khz v i = 0 v; a-weighted ? 87 ? db cs channel separation ? 82 ? db symbol parameter conditions min. typ. max. unit
2004 apr 22 56 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 18 timing v ddd =v dda(ad) =v dda(da) =v dda(hp) = 2.7 to 3.6 v; t amb = ? 20 to +85 c; all voltages referenced to ground; unless otherwise specified. symbol parameter conditions min. typ. max. unit system clock timing; note 1 t sys system clock cycle time f sys = 256f s 35 81 250 ns f sys = 384f s 23 54 170 ns f sys = 512f s 17 41 130 ns f sys = 768f s 17 27 90 ns t cwl system clock low time f sys < 19.2 mhz 0.3t sys ? 0.7t sys ns f sys 19.2 mhz 0.4t sys ? 0.6t sys ns t cwh system clock high time f sys < 19.2 mhz 0.3t sys ? 0.7t sys ns f sys 19.2 mhz 0.4t sys ? 0.6t sys ns serial interface input /output data timing (see fig.17) f bck bit clock frequency ?? 128f s hz t cy(bck) bit clock cycle time ?? 1 ? 128 t cy(s) (2) s t bckh bit clock high time 30 ?? ns t bckl bit clock low time 30 ?? ns t r rise time ?? 20 ns t f fall time ?? 20 ns t su(ws) word select set-up time 10 ?? ns t h(ws) word select hold time 10 ?? ns t su(datai) data input set-up time 10 ?? ns t h(datai) data input hold time 10 ?? ns t h(datao) data output hold time 0 ?? ns t d(datao-bck) data output to bit clock delay ?? 30 ns t d(datao-ws) data output to word select delay ?? 30 ns l3-bus interface timing (see figs 18 and 19 ) t r rise time note 3 ?? 10 ns/v t f fall time note 3 ?? 10 ns/v t cy(clk)l3 l3clock cycle time note 4 500 ?? ns t clk(l3)h l3clock high time note 4 250 ?? ns t clk(l3)l l3clock low time note 4 250 ?? ns t su(l3)a l3mode set-up time in address mode 190 ?? ns t h(l3)a l3mode hold time in address mode 190 ?? ns t su(l3)d l3mode set-up time in data transfer mode 190 ?? ns t h(l3)d l3mode hold time in data transfer mode 190 ?? ns
2004 apr 22 57 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 notes 1. the typical value of the timing is specified at 48 khz sampling frequency (see fig.16). 2. t cy(s) is the cycle time of the sample frequency. 3. in order to prevent digital noise interfering with the l3-bus communication, it is best to have the rise and fall times as short as possible. 4. when the sampling frequency is below 32 khz, the l3clock cycle must be limited to 1 ? 64fs cycle. 5. c b is the total capacitance of one bus line in pf. the maximum capacitive load for each bus line is 400 pf. 6. after this period, the firs t clock pulse is generated. 7. to be suppressed by the input filter. t stp(l3) l3mode stop time in data transfer mode 190 ?? ns t su(l3)da l3data set-up time in address and data transfer mode 190 ?? ns t h(l3)da l3data hold time in address and data transfer mode 30 ?? ns t d(l3)r l3data delay time in data transfer mode 0 ? 50 ns t dis(l3)r l3data disable time for read data 0 ? 50 ns i 2 c-bus interface timing; see fig.20 f scl scl clock frequency 0 ? 400 khz t low scl low time 1.3 ?? s t high scl high time 0.6 ?? s t r rise time sda and scl note 5 20 + 0.1c b ? 300 ns t f fall time sda and scl note 5 20 + 0.1c b ? 300 ns t hd;sta hold time start condition note 6 0.6 ?? s t su;sta set-up time repeated start 0.6 ?? s t su;sto set-up time stop condition 0.6 ?? s t buf bus free time between a stop and start condition 1.3 ?? s t su;dat data set-up time 100 ?? ns t hd;dat data hold time 0 ?? s t sp pulse width of spikes note 7 0 ? 50 ns c b capacitive load for each bus line ?? 400 pf symbol parameter conditions min. typ. max. unit
2004 apr 22 58 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 handbook, full pagewidth mgr984 t sys t cwh t cwl fig.16 timing of system clock. handbook, full pagewidth mgs756 ws bck datao datai t f t r t h(ws) t su(ws) t bckh t bckl t cy(bck) t h(datao) t su(datai) t h(datai) t d(datao-bck) t d(datao-ws) fig.17 serial interface input data timing.
2004 apr 22 59 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a fig.18 timing of address mode. handbook, full pagewidth t stp(l3) t su(l3)d t h(l3)da t su(l3)da t h(l3)d t cy(clk)l3 bit 0 l3mode l3clock l3data read l3data write bit 7 mgu015 t clk(l3)h t clk(l3)l t d(l3)r t dis(l3)r fig.19 timing of data transfer mode for write and read.
2004 apr 22 60 nxp semiconductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf s da s cl fig.20 timing of the i 2 c-bus transfer.
2004 apr 22 61 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 19 application information handbook, full pagewidth mgu537 100 f (16 v) 100 f (16 v) v dda v ddd blm31a601s blm31a601s + 3 v ground 2 (30) v adcn uda1380tt (uda1380hn) 31 (27) (23) 27 v ref v ref(hp) voutrhp voutlhp 5 (1) 4 (32) 20 (16) 24 (20) v adcp v ssa(hp) 47 47 f 18 (14) 17 (13) vinl vinr (21) 25 voutl 100 10 k 0 16 (12) sysclk l3data/sda l3clock/scl l3mode 19 (15) sel_l3_iic 12 (8) 11 (7) 10 (6) datai wsi bcki 15 (11) rtcb v dda v dda v ddd v dda(hp) reset 10 f (16 v) 47 f (16 v) 4.7 f (16 v) 100 nf (63 v) (5) 9 datao (4) 8 wso (3) 7 bcko (25) 29 (17) 21 0 (19) 23 (18) 22 100 f (16 v) 100 nf (63 v) 100 nf (63 v) 100 f (16 v) 100 47 k v dda(ad) v ddd v ssa(ad) v ssd 32 (28) 14 (10) 6 (2) 30 (26) 1 100 f (16 v) 100 nf (63 v) v dda 10 v ddd v dda(da) v ssa(da) 26 (22) 28 (24) 1 100 f (16 v) 100 nf (63 v) v dda left output voutr 100 10 k 47 f (16 v) right output headphone left input 13 (9) (16 v) 1 (29) 47 f right input (16 v) vinm 3 (31) 47 f micro- phone input system clock (16 v) fig.21 application diagram. pin numbers for uda1380hn in parentheses.
2004 apr 22 62 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 20 package outlines unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.85 0.30 0.19 0.20 0.09 11.1 10.9 6.2 6.0 0.65 8.3 7.9 0.78 0.48 8 0 o o 0.1 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot487-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 116 32 17 a a 1 a 2 l p detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm sot487 -1 a max. 1.1 pin 1 index
2004 apr 22 63 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 3.5 e 2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot617-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot617 -1 h vqfn32: plastic thermal enhanced very thin quad flat package; no leads; 3 2 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
2004 apr 22 64 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 21 soldering 21.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ?data handbook ic26; integrated circuit packages? (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering ca n still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 21.2 reflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215to270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) ? for all bga, htsson-t and ssop-t packages ? for packages with a thickness 2.5 mm ? for packages with a thickness < 2.5 mm and a volume 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 21.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): ? larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; ? smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will elim inate the need for removal of corrosive residues in most applications. 21.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limit ed to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2004 apr 22 65 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 21.5 suitability of surface m ount ic packages for wave and reflow soldering methods notes 1. for more detailed information on the bga packages refer to the ?(lf)bga application note ? (an01026); order a copy from your nxp semicond uctors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the ?data handbook ic26; integrated circuit packages; section: packing methods? . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2004 apr 22 66 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 22 data sheet status notes 1. please consult the most recently issued document before initiating or completing a design. 2. the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. the latest pr oduct status information is available on the internet at url http://www.nxp.com. document status (1) product status (2) definition objective data sheet development this document contains data from the objective specification for product development. preliminary data sheet qualification this document contains data from the preliminary specification. product data sheet production this document contains the product specification. 23 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semico nductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without lim itation - lost profits, lost savings, business interrup tion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semi conductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, lif e-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for incl usion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are fo r illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assi stance with ap plications or customer product design. it is customer?s sole responsibility to dete rmine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as for the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applications and products using nxp semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect.
2004 apr 22 67 nxp semico nductors product specification stereo audio coder-decoder for md, cd and mp3 uda1380 limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will c ause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeat ed exposure to lim iting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the general terms and conditions of comme rcial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconductors products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. quick reference data ? the quick refere nce data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semiconductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semicond uctors? warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond nxp semiconductors? standard warranty and nxp semiconductors? product specifications. 24 trademarks i 2 c-bus ? logo is a trademark of nxp b.v.
nxp semiconductors provides high performance mixed signal and standard product solutions that leverage its leadi ng rf, analog, power management, interface, security and digital processing expertise contact information for additional information please visit: http://www.nxp.com for sales offices addresses send e-mail to: salesaddresses@nxp.com ? nxp b.v. 2010 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liabilit y will be accepted by the publisher for any consequen ce of its use. publicat ion thereof d oes not con vey nor imply any license under patent- or other industrial or intellectual property rights. customer notification this data sheet was changed to reflect the new company name nxp semiconductors. no changes were made to the content, except for the legal definitions and disclaimers. printed in the netherlands r30/04/pp 68 date of release: 2004 apr 22 document order number: 9397 750 13108

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